| DESIGN FUNCTION AND QUANTITY | 3200 GATE, OR-AND |
| FEATURES PROVIDED | 3-STATE OUTPUT AND ELECTROSTATIC SENSITIVE AND PROGRAMMABLE AND W/CLOCK |
| INCLOSURE CONFIGURATION | QUAD-IN-LINE |
| INCLOSURE MATERIAL | PLASTIC |
| OPERATING TEMP RANGE | -40.0 TO 85.0 CELSIUS |
| OVERALL HEIGHT | 1.6 MILLIMETERS MAXIMUM |
| OVERALL LENGTH | 20.0 MILLIMETERS NOMINAL |
| OVERALL WIDTH | 20.0 MILLIMETERS NOMINAL |
| PART NAME ASSIGNED BY CONTROLLING AGENCY | HIGH PERFORMANCE CPLD |
| SPECIAL FEATURES | FULL IEEE STANDARD 1149.1 BOUNDARY-SCAN (JTAG); BUS-HOLD CIRCUITRY ON ALL USER PIN INPUTS; IN-SYSTEM PROGRAMMABLE; INDIVIDUAL OUTPUT ENABLE PER OUTPUT PIN WITH LOCAL INVERSION, LOCAL CLOCK INVERSION WITH 3 GLOBAL AND 1 PRODUCT-TERM CLOCKS; ADVANCED 0.35 MICRON FEATURE SIZE CMOS FAST FLASH TECHNOLOGY |
| TIME RATING PER CHACTERISTIC | 7.5 NANOSECONDS NOMINAL DELAY |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM INPUT |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 144 PIN |
| TERMINAL SURFACE TREATMENT | TIN |