| DESIGN FUNCTION AND QUANTITY | 1 MEMORY, ELECTRICALLY ERASABLE PROGRAMMABLE ROM AND 6000 GATE, LOGIC |
| CRITICALITY CODE JUSTIFICATION | CBBL |
| FEATURES PROVIDED | ELECTROSTATIC SENSITIVE |
| INCLOSURE CONFIGURATION | LEADED CHIP CARRIER |
| PART NAME ASSIGNED BY CONTROLLING AGENCY | HIGH DENSITY PROGRAMMABLE LOGIC DEVICE |
| PROPRIETARY CHARACTERISTICS | PACS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | COMPLEMENTARY-METAL OXIDE-SEMICONDUCTOR LOGIC |
| SPECIAL FEATURES | ITEM IS SELECTED FROM CAGE 66675 P/N ISPL-SI1032EA-100LT100 BASED ON REQUIREMENTS CONTAINED ON DRAWING 356A1409 |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 4.7 VOLTS MINIMUM TOTAL SUPPLY AND 5.2 VOLTS MAXIMUM TOTAL SUPPLY |
| STORAGE TEMP RANGE | -65.0 TO 150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 100 PIN |
| TEST DATA DOCUMENT | 89954-356A1409 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |