| BODY HEIGHT | 0.185 INCHES MAXIMUM |
| BODY LENGTH | 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.271 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | TO-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 4 RECEIVER |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND NEGATIVE OUTPUTS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC |
| INPUT CIRCUIT PATTERN | QUAD 2 INPUT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | -0.5 VOLTS MINIMUM POWER SOURCE AND 7.0 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TIME RATING PER CHACTERISTIC | 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 35.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |