| DESIGN FUNCTION AND QUANTITY | 2 ADDER, FULL, BINARY |
| BODY HEIGHT | 0.080 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.735 INCHES MINIMUM AND 0.800 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| FEATURES PROVIDED | HERMETICALLY SEALED AND BIPOLAR AND COMPLEMENTARY OUTPUTS |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC |
| INPUT CIRCUIT PATTERN | 8 INPUT |
| PROPRIETARY CHARACTERISTICS | PACS |
| OPERATING TEMP RANGE | +0.0/+70.0 DEG CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 16 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 18338-165668 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 45.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |