| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.120 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND-NOR |
| FEATURES PROVIDED | HERMETICALLY SEALED AND LOW POWER AND MONOLITHIC AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | GLASS AND METAL |
| INPUT CIRCUIT PATTERN | DUAL 5 INPUT |
| OPERATING TEMP RANGE | +0.0 TO 70.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 24.0 MILLIWATTS |
| PRECIOUS MATERIAL AND LOCATION | BODY GOLD AND TERMINALS GOLD |
| PRECIOUS MATERIAL | GOLD |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |
| STORAGE TEMP RANGE | -65.0 TO 125.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | GOLD |
| TIME RATING PER CHACTERISTIC | 30.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT |