| BODY HEIGHT | 0.165 INCHES MINIMUM AND 0.185 INCHES MAXIMUM |
| BODY OUTSIDE DIAMETER | 0.335 INCHES MINIMUM AND 0.370 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-99 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 GATE, NAND-NOR |
| FEATURES PROVIDED | MONOLITHIC AND HERMETICALLY SEALED AND LOW POWER AND POSITIVE OUTPUTS AND MEDIUM SPEED |
| INCLOSURE CONFIGURATION | CAN |
| INCLOSURE MATERIAL | GLASS AND METAL |
| INPUT CIRCUIT PATTERN | DUAL 2 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 250.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | RESISTOR-TRANSISTOR LOGIC |
| PRECIOUS MATERIAL | GOLD |
| PRECIOUS MATERIAL AND LOCATION | TERMINAL SURFACE GOLD |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | GOLD |
| TERMINAL TYPE AND QUANTITY | 8 PIN |
| TEST DATA DOCUMENT | 99971-7528158 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 4.0 VOLTS MAXIMUM POWER SOURCE |