| BODY HEIGHT | 0.035 INCHES MINIMUM AND 0.050 INCHES MAXIMUM |
| BODY LENGTH | 0.250 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.140 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, CLOCKED AND 2 FLIP-FLOP, J-K, MASTER SLAVE |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND MEDIUM POWER AND MEDIUM SPEED AND EDGE TRIGGERED AND W/CLEAR |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | GLASS AND METAL |
| INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
| MAXIMUM POWER DISSIPATION RATING | 220.0 MILLIWATTS |
| PRECIOUS MATERIAL AND LOCATION | TERMINAL AND BODY SURFACES GOLD |
| PRECIOUS MATERIAL | GOLD |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| SPECIAL FEATURES | FORMED LEADS; INSULATOR FURNISHED |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TIME RATING PER CHACTERISTIC | 39.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |